1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM) which utilizes a magneto resistive effect.
2. Description of the Related Art
A magnetic resistive random access memory which utilizes a tunneling magneto resistive effect (TMR) is characterized in storing data by using a magnetization state of an MTJ (Magnetic Tunnel Junction) element.
In recent years, there has been developed a yoke wiring technique (e.g., see Jpn. Pat. Appln. KOKAI No. 2003-209227) by which a yoke layer is provided around a write line for generating a magnetic field for the purpose of causing a magnetic field to efficiently act on an MTJ element.
(1) As one of the yoke wiring techniques, there has been known a process to form a yoke wiring by using RIE (Reactive Ion Etching).
FIG. 1 shows an example of a yoke wiring structure formed by RIE.
In a memory cell array section, a write word line 14A surrounded by an insulating layer (e.g., silicon oxide) 12A is arranged above a silicon substrate 11. An MTJ element MTJ is arranged above the write word line 14A. A write bit line 25A is arranged above the MTJ element MTJ through a cap layer 16. Yoke layers 26A and 26B are respectively arranged on side surfaces and a top surface of the write word bit line 25A.
Here, when forming the write bit line 25A by an RIE process, the workability of the write bit line 25A is very good. Further, the yoke layer 26A can be readily formed by a side wall process based on, e.g., CVD (Chemical Vapor Deposition) and RIE, and the yoke layer 26B can be likewise easily formed by, e.g., CVD and PEP (Photo Engraving process).
Usually, however, in the RIE process, the write bit line 25A is constituted of aluminum. In recent years, regarding the increase in demands for so-called low-temperature processes, it is well known that aluminium has poor coverage in a via hole.
In this case, in a via hole in a peripheral circuit section or a logic section, e.g., at an end section of the write bit line 25A, the coverage of aluminium as the write bit line 25A is deteriorated, thus there occurs a problem that the reliability is considerably lowered in a relationship with a signal line 14B.
Thus, in the magnetic random access memory, an adoption of a damascene process which can realize the low-temperature process without lowering the reliability in a via hole has been examined.
(2) A technique to form a yoke wiring by using a damascene process (including a dual damascene process) will now be described hereinafter.
FIG. 2 shows an example of a yoke wiring structure formed by the damascene process.
Insulating layers (e.g., silicon oxide) 12 and 13 are arranged on a silicon substrate 11. A plurality of wiring grooves are formed to the insulating layer 13, and a write word line 14A and a signal line 14B are arranged in these wiring grooves. An MTJ element MTJ is arranged on the write word line 14A. A write bit line 25 is arranged above the MTJ element MTJ through a cap layer 16. Yoke layers 24 and 26 are respectively arranged on side surfaces and a top surface of the write bit line 25. The write bit line 25 is filled in a wiring groove 20 formed to an insulating layer (e.g., silicon oxide) 19.
According to this damascene process, since copper as the write bit line 25 is completely filled in a via hole 17 in a peripheral circuit section or a logic section, e.g., at an end section of the write bit line 25, the reliability can be greatly improved in a relationship with the signal line 14B.
However, the damascene process has a problem.
In the magnetic random access memory, in order to reduce a value of a write current flowing through the write bit line 25, a magnetic field generated by the write current must be caused to efficiently act on the MTJ element MTJ.
As one of such methods, there has been an attempt to shorten a distance between the MTJ element MTJ and the write bit line 25.
However, as shown in, e.g., FIG. 3, reducing a thickness X1 of a cap layer 16 in order to shorten a distance between the MTJ element MTJ and the write bit line 25 may cause side surfaces of the MTJ element MTJ to be exposed due to over-etching at the time of RIE to form the wiring groove 20 to the insulting layer 19. In this case, when an electroconductive layer is filled in the wiring groove 20, a pin layer 31 and a free layer 32 of the MTJ element MTJ short-circuit, thereby generating a bit defect.
It is apparent that such a phenomenon will become a serious problem in future with a demand to set the thickness X1 of the cap layer 16 to be 5 to 100 nm, whilst a thickness of the insulating layer 19 is 300 to 500 nm and an over-etching quantity (margin) of the insulating layer 19 in RIE is approximately 10 to 30% of the thickness of the insulating layer 19.
It is to be noted that sufficiently increasing a thickness X2 of the cap layer 16 as shown in FIG. 4 can avoid such a problem, but if this is done, a distance between the MTJ element MTJ and the write bit line 25 becomes too large, which is counter-productive.